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What are the key sales KPIs for the Semiconductor Foundry industry in 2027?

📖 2,431 words🗓️ Published Jun 20, 2026 · Updated May 30, 2026

Direct Answer

The nine KPIs that actually run a semiconductor foundry in 2027 are: Wafer Revenue ($B), Advanced-Node Mix % (sub-7nm / sub-3nm / sub-2nm), Capacity Utilization %, ASP per 12-inch Wafer Equivalent, Gross Margin %, CapEx Intensity % of Revenue, HBM/CoWoS Advanced-Packaging Revenue, Top-10 Customer Concentration %, and Tape-Out Count + Node-Yield Ramp Time. Together they answer the only three questions the board cares about: are you booked through next year, is the leading-edge mix carrying the P&L, and is CapEx pacing ahead of demand without blowing the depreciation curve.

> TL;DR — A foundry is a capital-allocation machine disguised as a manufacturer. TSMC books ~74% of wafer revenue from 7nm and below, runs ~$52–56B of 2026 CapEx (roughly 38–40% of revenue), and sells 2nm wafers at a ~50% premium to 3nm — and that's the formula. If advanced-node mix slips below 60%, capacity utilization drops under 80%, or CoWoS lead times collapse from 50+ weeks back toward parity, the depreciation tail eats the margin. Track the nine KPIs monthly, re-baseline CapEx every quarter against confirmed customer tape-outs, and treat HBM packaging as a separate P&L — that is how TSMC, Samsung Foundry, and GlobalFoundries are now run.

Why Semiconductor Foundries Work Differently

A pure-play foundry is not a chip company — it is a leased-asset business where the asset happens to be a $20B fab. Four mechanics make it its own category.

Capital-intensity-first economics. A leading-edge fab costs $20–25B, depreciates over 5–7 years on the books, and must run above ~80% utilization to clear the depreciation hurdle. TSMC's 2026 CapEx guidance of $52–56B is roughly 38–40% of revenue — a ratio no other industry tolerates. That means every node decision is a 5-year capital bet made 24–36 months before the first revenue wafer ships.

Node-cycle revenue stacking. Foundry revenue is not a single S-curve — it is a stack of overlapping S-curves. In Q3 2025 TSMC's wafer revenue split was roughly 3nm at 23%, 5nm at 37%, 7nm at 14%, and trailing nodes at the rest, with 2nm cumulative revenue projected to surpass 3nm and 5nm by Q3 2026. The operating motion is keeping the leading-edge ramping while the prior node still pays for the building.

Customer-concentration as a feature, not a bug. TSMC's top-10 customers account for ~70–75% of revenue, with Nvidia at ~22% and Apple at ~16–18% in 2026 after Nvidia overtook Apple as the #1 account. Broadcom (~11%), AMD (~8%), Qualcomm, and MediaTek round out the next tier. That concentration is what funds the CapEx — multi-year hyperscaler and Apple commitments let TSMC pre-sell capacity 18–24 months out. Lose one of the top three and the fab plan unravels.

Advanced packaging as the second business. CoWoS (chip-on-wafer-on-substrate) is now the binding constraint on AI compute. TSMC's CoWoS capacity is scaling from ~35K wafers/month in late 2024 to ~130K/month by end of 2026, with lead times sitting at 50+ weeks through Q1 2026. The CFO's question is no longer just "wafer revenue per node" — it's "advanced-packaging revenue per CoWoS slot, and who has 24-month allocation."

The 9 KPIs, In Depth

1. Wafer Revenue ($B). The headline number, reported quarterly by node and by platform (HPC, smartphone, IoT, auto). TSMC is on track for ~$140B+ of 2026 revenue, Samsung Foundry estimated at ~$18–22B, GlobalFoundries at ~$6.5B (run-rate from $1.63B Q1 2026), UMC at ~$7B, SMIC at ~$8B, Intel Foundry still pre-revenue at scale. Always split by node — blended wafer revenue hides the leading-edge story.

2. Advanced-Node Mix % (sub-7nm / sub-3nm / sub-2nm). Share of wafer revenue from 7nm-and-below, 3nm-and-below, and 2nm. TSMC runs at ~74% sub-7nm, ~23% sub-3nm entering 2026, ramping 2nm to ~60K wafers/month by year-end. Samsung Foundry's sub-7nm mix is closer to 35–40%. GlobalFoundries deliberately exited the leading-edge race in 2018 — its sub-7nm mix is 0%, by design. Anything under 50% sub-7nm at a pure-play means you are a mature-node fab whether you admit it or not.

3. Capacity Utilization %. Wafer starts divided by installed capacity, reported by node. 80% is the depreciation breakeven for a leading-edge fab; below 70% the node loses money. TSMC is reportedly fully booked on 3nm through 2026 and 2nm sold out through 2027 at allocation. GlobalFoundries Q1 2026 utilization recovered into the mid-80s after a 2024 trough in the 70s. SMIC's leading-edge utilization is constrained by equipment sanctions, not demand.

4. ASP per 12-inch Wafer Equivalent. Average selling price normalized to 300mm. 2nm wafers price at roughly $30K, ~50% above 3nm at ~$20K, with 3nm itself ~30% above 5nm. TSMC has guided to annual price increases on advanced nodes for four consecutive years starting 2026. Mature-node ASPs at GlobalFoundries and UMC run $3–6K depending on process. Blended ASP is meaningless — track it per node, per customer tier.

5. Gross Margin %. The single best indicator of node maturity and pricing power. TSMC's 2026 gross margin is running at ~57–59%. GlobalFoundries reported 27.6% IFRS / 29.0% non-IFRS gross margin in Q1 2026. Samsung Foundry is estimated at single-digit-to-low-teens as Exynos and external customers under-fill its 3nm/2nm capacity. Intel Foundry runs deeply negative. A 30-percentage-point gross margin gap between TSMC and the field is the entire investment thesis.

6. CapEx Intensity % of Revenue. Annual CapEx divided by annual revenue. The healthy band for a leading-edge foundry is 30–50%. TSMC's $52–56B 2026 CapEx is ~38–40% of revenue — high but funded by pre-sold capacity. Samsung Foundry runs in the 40–50% zone. Intel Foundry's CapEx as a percent of revenue is meaningless because the denominator is too small. CapEx intensity below 25% at a leading-edge player means you are under-investing and will lose the next node.

7. HBM/CoWoS Advanced-Packaging Revenue. A separate P&L line at TSMC and the binding constraint on AI compute. CoWoS capacity is scaling from ~35K wafers/month in late 2024 to ~130K/month by end of 2026. HBM3E pricing is up ~30% year-over-year in 2026. Nvidia is the dominant CoWoS customer; AMD, Broadcom custom AI silicon, and AWS Trainium take the rest. Advanced-packaging revenue is projected to cross ~$15B at TSMC in 2026, growing faster than wafer revenue.

8. Top-10 Customer Concentration %. Share of revenue from the ten largest accounts. TSMC sits at ~70–75%, with Nvidia ~22%, Apple ~16–18%, Broadcom ~11%, AMD ~8%, Qualcomm and MediaTek mid-single-digits each. GlobalFoundries' top-3 (Qualcomm, AMD, NXP) account for ~40%+. SMIC's top customers are skewed to domestic Chinese fabless. Concentration is the funding mechanism — Apple and Nvidia pre-commit billions to lock allocation, which is what makes the CapEx bankable.

9. Tape-Out Count + Node-Yield Ramp Time. Tape-outs are the leading indicator — design starts on a node 18–24 months before volume revenue. TSMC reported >450 new tape-outs on N3 family through 2025 and >200 expected on N2 through 2027. Node-yield ramp time — from first silicon to >70% defect-density-corrected yield — is now 18–24 months for 3nm and likely 24–30 months for 2nm with GAA. Samsung's 3nm GAA ramp slipped past 30 months and is the reason its external customer mix is thin.

Real Operators

TSMC is the benchmark — ~$140B+ 2026 revenue, ~57–59% gross margin, ~38–40% CapEx intensity, ~74% advanced-node mix, the only foundry running 2nm at volume. Samsung Foundry is the distant #2 by revenue (~$18–22B est.) but the only credible second source on leading-edge — its 2nm ramp determines whether the industry has a duopoly or a monopoly. Intel Foundry is the wildcard — 18A entered risk production in 2025 with Microsoft and DoD as anchor customers, but external revenue is still negligible. GlobalFoundries owns the differentiated specialty-node niche — FDX, RF-SOI, silicon photonics — at ~$6.5B revenue and a deliberate no-bleeding-edge strategy. SMIC is China's national champion at ~$8B, leading-edge capped by equipment sanctions but dominant in mature-node domestic demand. UMC runs ~$7B in pure mature-node analog and specialty. Tower Semiconductor (now operating closely with Intel Foundry after the 2024 deal collapse and subsequent partnership) is the analog/RF specialty leader. Vanguard International Semiconductor (TSMC-affiliated) handles 8-inch mature nodes. Powerchip Semiconductor Manufacturing Corp (PSMC) is the Taiwan-based DRAM-and-foundry hybrid. Hua Hong Semiconductor is the #2 Chinese pure-play behind SMIC.

Failure Modes

The four that kill foundries. (1) Node-yield slip — Samsung's 3nm GAA ramp ran 30+ months and the customer pipeline thinned. A 6-month yield miss on the leading edge can cost a generation of design wins because customers move their next tape-out elsewhere. (2) CapEx-ahead-of-demand — building a $20B fab 24 months before customers commit creates a depreciation cliff. Intel Foundry is currently living this risk. (3) Customer-concentration unwind — if Apple or Nvidia diversifies allocation to Samsung or Intel, TSMC's CapEx model gets re-rated overnight. The 2026 Nvidia-over-Apple flip showed how fast the mix can shift. (4) Geopolitical capacity stranding — SMIC's leading-edge ambitions are capped by U.S. export controls, and TSMC's Arizona fabs run at a structural cost premium versus Taiwan. Foundry CapEx is now a geopolitical bet, not just a market bet.

Reporting Cadence

Daily: wafer starts by node, equipment availability, yield-loss flags from in-line metrology. Weekly: tape-out funnel, customer allocation requests, CoWoS slot booking status. Monthly: wafer revenue by node and platform, capacity utilization by fab, ASP trends by customer, gross margin walk. Quarterly: full P&L, CapEx pacing versus plan, advanced-node mix, top-10 customer concentration, HBM/CoWoS revenue split, next-node yield-ramp milestones for the earnings call.

30/60/90 Day Plan

Days 1–30: instrument the nine KPIs end-to-end against MES, ERP, and customer-allocation systems. Reconcile wafer-out counts between manufacturing, finance, and customer-shipped reports — they will not match and that gap is the first finding. Establish baseline gross margin per node and ASP per customer tier. Pull the last eight quarters of CoWoS allocation versus customer demand and quantify the gap.

Days 31–60: ship the advanced-node mix and CapEx-intensity dashboards. Wire CapEx to the multi-year fab build schedule on one side and confirmed customer tape-out commitments on the other. Identify the next-node yield-ramp critical path — equipment install, process qualification, customer PDK release — and build a weekly stoplight against the published ramp curve.

Days 61–90: run the first quarterly top-10 customer review. Model each top-10 account's 24-month wafer demand by node and stress-test concentration risk if any one of the top three reallocates 25% of volume. Re-baseline 2027 CapEx against the demand model and present a revised operating plan to the CFO with monthly checkpoints on utilization, gross margin, and CoWoS revenue.

FAQ

What is the most important single KPI for a semiconductor foundry in 2027? Advanced-node mix percentage (sub-7nm, sub-3nm, sub-2nm) is arguably the most critical. It directly drives wafer revenue premiums and determines whether capacity utilization stays above 80%. If this mix falls below 60%, the depreciation burden from leading-edge fabs can quickly erode gross margins.

How does capacity utilization affect foundry profitability? Capacity utilization measures how much of a fab's potential output is actually being used. In 2027, a utilization rate below 80% typically means fixed costs like depreciation start eating into margins, while rates above 90% often signal pricing power and tight supply. Most leading foundries target the 85–95% range for healthy profitability.

Why is CapEx intensity a key KPI for foundries? CapEx intensity (capital expenditure as a percentage of revenue) reflects how aggressively a foundry is investing in next-generation nodes and capacity. In 2027, industry leaders like TSMC run around 38–40% CapEx intensity, while smaller players may be in the 20–30% range. Too high can strain cash flow; too low risks falling behind on technology.

What does "ASP per 12-inch wafer equivalent" tell you? This KPI tracks the average selling price normalized to a standard 300mm wafer. It reveals pricing power and product mix shifts—2nm wafers, for example, command roughly a 50% premium over 3nm. A rising ASP typically indicates a richer mix of advanced-node and specialty products.

How do HBM and advanced-packaging revenue matter for foundries? HBM (High Bandwidth Memory) and CoWoS (Chip-on-Wafer-on-Substrate) packaging revenue is increasingly separated as its own P&L line. In 2027, this segment can contribute 5–15% of total foundry revenue for leaders, with lead times often exceeding 50 weeks. It's a high-growth, high-margin area that diversifies beyond traditional wafer sales.

What is the significance of tape-out count and node-yield ramp time? Tape-out count measures the number of new chip designs entering production, indicating future demand. Node-yield ramp time tracks how quickly a new process reaches acceptable yield levels. In 2027, a fast ramp (under 12 months) can secure early customer commitments and premium pricing, while delays risk losing market share to competitors.

flowchart TD A[Customer Tape-Out] --> B{Node Choice} B -->|2nm/3nm Leading-Edge| C[Premium ASP $20-30K/wafer] B -->|5nm/7nm Mainstream| D[Mid ASP $10-17K/wafer] B -->|Mature 28nm+| E[Low ASP $3-6K/wafer] C --> F[Requires CoWoS Slot?] F -->|Yes - AI/HPC| G[Advanced Packaging Revenue] F -->|No - Mobile SoC| H[Wafer-Only Revenue] D --> H E --> H G --> I[Capacity Utilization] H --> I I --> J{Utilization over 80%?} J -->|Yes| K[Gross Margin 50%+] J -->|No| L[Depreciation Drag - Margin Compression] K --> M[CapEx Reinvestment 35-45% of Revenue] M --> N[Next-Node Fab Build] N --> A

flowchart TD A[Daily Fab Telemetry] --> B[Wafer Starts + Yield + Equipment Uptime] B --> C[Weekly Allocation Review] C --> D[Tape-Out Funnel + CoWoS Bookings + Customer Asks] D --> E[Monthly Business Review] E --> F[Wafer Revenue by Node + Utilization + ASP + GM Walk] F --> G[Quarterly Earnings + Board] G --> H[Full P&L + CapEx Pacing + Node Mix + Top-10 Concentration + HBM] H --> I[Re-baseline Node Roadmap + CapEx + Customer Commitments] I --> A

Related on PULSE

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Sources

SEMI — World Fab Forecast (Q1 2026 update)
TrendForce — TSMC 3nm and 2nm Capacity Reports (2025–2026)
TechInsights — Advanced Node Yield and Ramp Analysis
Morgan Stanley Research — TSMC 2026 Revenue Mix and Customer Concentration
Taiwan Semiconductor Manufacturing Co. — Form 6-K Q1 2026 Earnings
GlobalFoundries Inc. — Form 6-K Q1 2026 Earnings (SEC filing 0001709048)
Samsung Electronics Co. Ltd. — Annual Report (DART filing, ticker 005930.KS)
Intel Corporation — Form 10-K (Intel Foundry segment)
Bloomberg Intelligence — Global Semiconductor Foundry Outlook 2026
IC Insights / McClean Report — Foundry Market Share and CapEx Tracker

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![What are the key sales KPIs for the Semiconductor Foundry industry in 2027?](/assets/qa/gb0239.jpg)

### Direct Answer

![silicon wafer close up](/assets/qa/ik0363.jpg)

The nine KPIs that actually run a semiconductor foundry in 2027 are: **Wafer Revenue ($B)**, **Advanced-Node Mix % (sub-7nm / sub-3nm / sub-2nm)**, **Capacity Utilization %**, **ASP per 12-inch Wafer Equivalent**, **Gross Margin %**, **CapEx Intensity % of Revenue**, **HBM/CoWoS Advanced-Packaging Revenue**, **Top-10 Customer Concentration %**, and **Tape-Out Count + Node-Yield Ramp Time**. Together they answer the only three questions the board cares about: are you booked through next year, is the leading-edge mix carrying the P&L, and is CapEx pacing ahead of demand without blowing the depreciation curve.

> **TL;DR** — A foundry is a capital-allocation machine disguised as a manufacturer. TSMC books ~74% of wafer revenue from 7nm and below, runs ~$52–56B of 2026 CapEx (roughly 38–40% of revenue), and sells 2nm wafers at a ~50% premium to 3nm — and that's the formula. If advanced-node mix slips below 60%, capacity utilization drops under 80%, or CoWoS lead times collapse from 50+ weeks back toward parity, the depreciation tail eats the margin. Track the nine KPIs monthly, re-baseline CapEx every quarter against confirmed customer tape-outs, and treat HBM packaging as a separate P&L — that is how TSMC, Samsung Foundry, and GlobalFoundries are now run.

## Why Semiconductor Foundries Work Differently

![TSMC chip fabrication plant](https://image.cnbcfm.com/api/v1/image/108075517-1734067155174-TSMC_12.jpg?w=1920&h=1080)


A pure-play foundry is not a chip company — it is a leased-asset business where the asset happens to be a $20B fab. Four mechanics make it its own category.

**Capital-intensity-first economics.** A leading-edge fab costs $20–25B, depreciates over 5–7 years on the books, and must run above ~80% utilization to clear the depreciation hurdle. TSMC's 2026 CapEx guidance of **$52–56B** is roughly **38–40% of revenue** — a ratio no other industry tolerates. That means every node decision is a 5-year capital bet made 24–36 months before the first revenue wafer ships.

**Node-cycle revenue stacking.** Foundry revenue is not a single S-curve — it is a stack of overlapping S-curves. In Q3 2025 TSMC's wafer revenue split was roughly **3nm at 23%, 5nm at 37%, 7nm at 14%, and trailing nodes at the rest**, with 2nm cumulative revenue projected to **surpass 3nm and 5nm by Q3 2026**. The operating motion is keeping the leading-edge ramping while the prior node still pays for the building.

**Customer-concentration as a feature, not a bug.** TSMC's top-10 customers account for **~70–75% of revenue**, with **Nvidia at ~22% and Apple at ~16–18% in 2026** after Nvidia overtook Apple as the #1 account. Broadcom (~11%), AMD (~8%), Qualcomm, and MediaTek round out the next tier. That concentration is what funds the CapEx — multi-year hyperscaler and Apple commitments let TSMC pre-sell capacity 18–24 months out. Lose one of the top three and the fab plan unravels.

**Advanced packaging as the second business.** CoWoS (chip-on-wafer-on-substrate) is now the binding constraint on AI compute. TSMC's CoWoS capacity is scaling from ~35K wafers/month in late 2024 to **~130K/month by end of 2026**, with lead times sitting at **50+ weeks** through Q1 2026. The CFO's question is no longer just "wafer revenue per node" — it's "advanced-packaging revenue per CoWoS slot, and who has 24-month allocation."

## The 9 KPIs, In Depth

![sales KPI dashboard chart](https://image.pollinations.ai/prompt/realistic%20editorial%20photograph%20of%20sales%20KPI%20dashboard%20chart%2C%20natural%20light%2C%20no%20text%2C%20no%20watermark?width=1200&height=675&nologo=true&model=flux&seed=8401)


**1. Wafer Revenue ($B).** The headline number, reported quarterly by node and by platform (HPC, smartphone, IoT, auto). **TSMC** is on track for ~**$140B+ of 2026 revenue**, **Samsung Foundry** estimated at ~**$18–22B**, **GlobalFoundries** at ~**$6.5B** (run-rate from $1.63B Q1 2026), **UMC** at ~$7B, **SMIC** at ~$8B, **Intel Foundry** still pre-revenue at scale. Always split by node — blended wafer revenue hides the leading-edge story.

**2. Advanced-Node Mix % (sub-7nm / sub-3nm / sub-2nm).** Share of wafer revenue from 7nm-and-below, 3nm-and-below, and 2nm. TSMC runs at **~74% sub-7nm**, **~23% sub-3nm** entering 2026, ramping 2nm to **~60K wafers/month** by year-end. Samsung Foundry's sub-7nm mix is closer to **35–40%**. GlobalFoundries deliberately exited the leading-edge race in 2018 — its sub-7nm mix is **0%**, by design. Anything under 50% sub-7nm at a pure-play means you are a mature-node fab whether you admit it or not.

**3. Capacity Utilization %.** Wafer starts divided by installed capacity, reported by node. **80% is the depreciation breakeven** for a leading-edge fab; below 70% the node loses money. TSMC is reportedly **fully booked on 3nm through 2026** and **2nm sold out through 2027** at allocation. GlobalFoundries Q1 2026 utilization recovered into the **mid-80s** after a 2024 trough in the 70s. SMIC's leading-edge utilization is constrained by equipment sanctions, not demand.

**4. ASP per 12-inch Wafer Equivalent.** Average selling price normalized to 300mm. **2nm wafers price at roughly $30K**, ~**50% above 3nm at ~$20K**, with 3nm itself ~30% above 5nm. TSMC has guided to **annual price increases on advanced nodes for four consecutive years starting 2026**. Mature-node ASPs at GlobalFoundries and UMC run **$3–6K** depending on process. Blended ASP is meaningless — track it per node, per customer tier.

**5. Gross Margin %.** The single best indicator of node maturity and pricing power. **TSMC's 2026 gross margin is running at ~57–59%**. **GlobalFoundries** reported **27.6% IFRS / 29.0% non-IFRS gross margin in Q1 2026**. **Samsung Foundry** is estimated at **single-digit-to-low-teens** as Exynos and external customers under-fill its 3nm/2nm capacity. **Intel Foundry** runs **deeply negative**. A 30-percentage-point gross margin gap between TSMC and the field is the entire investment thesis.

**6. CapEx Intensity % of Revenue.** Annual CapEx divided by annual revenue. The healthy band for a leading-edge foundry is **30–50%**. TSMC's **$52–56B 2026 CapEx is ~38–40% of revenue** — high but funded by pre-sold capacity. Samsung Foundry runs in the **40–50%** zone. Intel Foundry's CapEx as a percent of revenue is meaningless because the denominator is too small. CapEx intensity below 25% at a leading-edge player means you are under-investing and will lose the next node.

**7. HBM/CoWoS Advanced-Packaging Revenue.** A separate P&L line at TSMC and the binding constraint on AI compute. **CoWoS capacity** is scaling from **~35K wafers/month in late 2024 to ~130K/month by end of 2026**. HBM3E pricing is up **~30% year-over-year** in 2026. Nvidia is the dominant CoWoS customer; AMD, Broadcom custom AI silicon, and AWS Trainium take the rest. Advanced-packaging revenue is projected to cross **~$15B at TSMC in 2026**, growing faster than wafer revenue.

**8. Top-10 Customer Concentration %.** Share of revenue from the ten largest accounts. **TSMC sits at ~70–75%**, with **Nvidia ~22%, Apple ~16–18%, Broadcom ~11%, AMD ~8%, Qualcomm and MediaTek mid-single-digits each**. GlobalFoundries' top-3 (Qualcomm, AMD, NXP) account for **~40%+**. SMIC's top customers are skewed to domestic Chinese fabless. Concentration is the funding mechanism — Apple and Nvidia pre-commit billions to lock allocation, which is what makes the CapEx bankable.

**9. Tape-Out Count + Node-Yield Ramp Time.** Tape-outs are the leading indicator — design starts on a node 18–24 months before volume revenue. TSMC reported **>450 new tape-outs on N3 family** through 2025 and **>200 expected on N2** through 2027. Node-yield ramp time — from first silicon to >70% defect-density-corrected yield — is now **18–24 months for 3nm** and likely **24–30 months for 2nm with GAA**. Samsung's 3nm GAA ramp slipped past **30 months** and is the reason its external customer mix is thin.

```mermaid
flowchart TD
    A[Customer Tape-Out] --> B{Node Choice}
    B -->|2nm/3nm Leading-Edge| C[Premium ASP $20-30K/wafer]
    B -->|5nm/7nm Mainstream| D[Mid ASP $10-17K/wafer]
    B -->|Mature 28nm+| E[Low ASP $3-6K/wafer]
    C --> F[Requires CoWoS Slot?]
    F -->|Yes - AI/HPC| G[Advanced Packaging Revenue]
    F -->|No - Mobile SoC| H[Wafer-Only Revenue]
    D --> H
    E --> H
    G --> I[Capacity Utilization]
    H --> I
    I --> J{Utilization over 80%?}
    J -->|Yes| K[Gross Margin 50%+]
    J -->|No| L[Depreciation Drag - Margin Compression]
    K --> M[CapEx Reinvestment 35-45% of Revenue]
    M --> N[Next-Node Fab Build]
    N --> A
```

## Real Operators

**TSMC** is the benchmark — ~$140B+ 2026 revenue, ~57–59% gross margin, ~38–40% CapEx intensity, ~74% advanced-node mix, the only foundry running 2nm at volume. **Samsung Foundry** is the distant #2 by revenue (~$18–22B est.) but the only credible second source on leading-edge — its 2nm ramp determines whether the industry has a duopoly or a monopoly. **Intel Foundry** is the wildcard — 18A entered risk production in 2025 with Microsoft and DoD as anchor customers, but external revenue is still negligible. **GlobalFoundries** owns the differentiated specialty-node niche — FDX, RF-SOI, silicon photonics — at ~$6.5B revenue and a deliberate no-bleeding-edge strategy. **SMIC** is China's national champion at ~$8B, leading-edge capped by equipment sanctions but dominant in mature-node domestic demand. **UMC** runs ~$7B in pure mature-node analog and specialty. **Tower Semiconductor** (now operating closely with Intel Foundry after the 2024 deal collapse and subsequent partnership) is the analog/RF specialty leader. **Vanguard International Semiconductor** (TSMC-affiliated) handles 8-inch mature nodes. **Powerchip Semiconductor Manufacturing Corp (PSMC)** is the Taiwan-based DRAM-and-foundry hybrid. **Hua Hong Semiconductor** is the #2 Chinese pure-play behind SMIC.

## Failure Modes

The four that kill foundries. **(1) Node-yield slip** — Samsung's 3nm GAA ramp ran 30+ months and the customer pipeline thinned. A 6-month yield miss on the leading edge can cost a generation of design wins because customers move their next tape-out elsewhere. **(2) CapEx-ahead-of-demand** — building a $20B fab 24 months before customers commit creates a depreciation cliff. Intel Foundry is currently living this risk. **(3) Customer-concentration unwind** — if Apple or Nvidia diversifies allocation to Samsung or Intel, TSMC's CapEx model gets re-rated overnight. The 2026 Nvidia-over-Apple flip showed how fast the mix can shift. **(4) Geopolitical capacity stranding** — SMIC's leading-edge ambitions are capped by U.S. export controls, and TSMC's Arizona fabs run at a structural cost premium versus Taiwan. Foundry CapEx is now a geopolitical bet, not just a market bet.

## Reporting Cadence

**Daily:** wafer starts by node, equipment availability, yield-loss flags from in-line metrology. **Weekly:** tape-out funnel, customer allocation requests, CoWoS slot booking status. **Monthly:** wafer revenue by node and platform, capacity utilization by fab, ASP trends by customer, gross margin walk. **Quarterly:** full P&L, CapEx pacing versus plan, advanced-node mix, top-10 customer concentration, HBM/CoWoS revenue split, next-node yield-ramp milestones for the earnings call.

```mermaid
flowchart TD
    A[Daily Fab Telemetry] --> B[Wafer Starts + Yield + Equipment Uptime]
    B --> C[Weekly Allocation Review]
    C --> D[Tape-Out Funnel + CoWoS Bookings + Customer Asks]
    D --> E[Monthly Business Review]
    E --> F[Wafer Revenue by Node + Utilization + ASP + GM Walk]
    F --> G[Quarterly Earnings + Board]
    G --> H[Full P&L + CapEx Pacing + Node Mix + Top-10 Concentration + HBM]
    H --> I[Re-baseline Node Roadmap + CapEx + Customer Commitments]
    I --> A
```

## 30/60/90 Day Plan

**Days 1–30:** instrument the nine KPIs end-to-end against MES, ERP, and customer-allocation systems. Reconcile wafer-out counts between manufacturing, finance, and customer-shipped reports — they will not match and that gap is the first finding. Establish baseline gross margin per node and ASP per customer tier. Pull the last eight quarters of CoWoS allocation versus customer demand and quantify the gap.

**Days 31–60:** ship the advanced-node mix and CapEx-intensity dashboards. Wire CapEx to the multi-year fab build schedule on one side and confirmed customer tape-out commitments on the other. Identify the next-node yield-ramp critical path — equipment install, process qualification, customer PDK release — and build a weekly stoplight against the published ramp curve.

**Days 61–90:** run the first quarterly top-10 customer review. Model each top-10 account's 24-month wafer demand by node and stress-test concentration risk if any one of the top three reallocates 25% of volume. Re-baseline 2027 CapEx against the demand model and present a revised operating plan to the CFO with monthly checkpoints on utilization, gross margin, and CoWoS revenue.

## FAQ

**What is the most important single KPI for a semiconductor foundry in 2027?**  
Advanced-node mix percentage (sub-7nm, sub-3nm, sub-2nm) is arguably the most critical. It directly drives wafer revenue premiums and determines whether capacity utilization stays above 80%. If this mix falls below 60%, the depreciation burden from leading-edge fabs can quickly erode gross margins.

**How does capacity utilization affect foundry profitability?**  
Capacity utilization measures how much of a fab's potential output is actually being used. In 2027, a utilization rate below 80% typically means fixed costs like depreciation start eating into margins, while rates above 90% often signal pricing power and tight supply. Most leading foundries target the 85–95% range for healthy profitability.

**Why is CapEx intensity a key KPI for foundries?**  
CapEx intensity (capital expenditure as a percentage of revenue) reflects how aggressively a foundry is investing in next-generation nodes and capacity. In 2027, industry leaders like TSMC run around 38–40% CapEx intensity, while smaller players may be in the 20–30% range. Too high can strain cash flow; too low risks falling behind on technology.

**What does "ASP per 12-inch wafer equivalent" tell you?**  
This KPI tracks the average selling price normalized to a standard 300mm wafer. It reveals pricing power and product mix shifts—2nm wafers, for example, command roughly a 50% premium over 3nm. A rising ASP typically indicates a richer mix of advanced-node and specialty products.

**How do HBM and advanced-packaging revenue matter for foundries?**  
HBM (High Bandwidth Memory) and CoWoS (Chip-on-Wafer-on-Substrate) packaging revenue is increasingly separated as its own P&L line. In 2027, this segment can contribute 5–15% of total foundry revenue for leaders, with lead times often exceeding 50 weeks. It's a high-growth, high-margin area that diversifies beyond traditional wafer sales.

**What is the significance of tape-out count and node-yield ramp time?**  
Tape-out count measures the number of new chip designs entering production, indicating future demand. Node-yield ramp time tracks how quickly a new process reaches acceptable yield levels. In 2027, a fast ramp (under 12 months) can secure early customer commitments and premium pricing, while delays risk losing market share to competitors.

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## Sources

- SEMI — World Fab Forecast (Q1 2026 update)
- TrendForce — TSMC 3nm and 2nm Capacity Reports (2025–2026)
- TechInsights — Advanced Node Yield and Ramp Analysis
- Morgan Stanley Research — TSMC 2026 Revenue Mix and Customer Concentration
- Taiwan Semiconductor Manufacturing Co. — Form 6-K Q1 2026 Earnings
- GlobalFoundries Inc. — Form 6-K Q1 2026 Earnings (SEC filing 0001709048)
- Samsung Electronics Co. Ltd. — Annual Report (DART filing, ticker 005930.KS)
- Intel Corporation — Form 10-K (Intel Foundry segment)
- Bloomberg Intelligence — Global Semiconductor Foundry Outlook 2026
- IC Insights / McClean Report — Foundry Market Share and CapEx Tracker

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